This file is designed to give a basic overview of the bus
\nfound in most IBM clone computers, often referred to as the XT or
\nAT bus. The AT version of the bus is upwardly compatible, which
\nmeans that cards designed to work on an XT bus will work on an AT
\nbus. This bus was produced for many years without any formal
\nstandard. In recent years, a more formal standard called the ISA
\nbus (Industry Standard Architecture) has been created, with an
\nextension called the EISA (Extended ISA) bus also now as a
\nstandard. The EISA bus extensions will not be detailed here.<\/p>\n
This file is not intended to be a thorough coverage of the
\nstandard. It is for informational purposes only, and is intended
\nto give designers and hobbyists sufficient information to design
\ntheir own XT and AT compatible cards.<\/p>\n
Physical Design:<\/strong><\/p>\n ISA cards can be either 8-bit or 16-bit. 8-bit cards only uses 8-bit card:<\/strong><\/p>\n 16-bit card:<\/strong><\/p>\n Signal Descriptions:<\/strong><\/p>\n +5, -5, +12, -12<\/strong><\/p>\n Power supplies. -5 is often not implemented.<\/p>\n AEN<\/strong><\/p>\n Address Enable. This is asserted when a DMAC has control of BALE<\/strong><\/p>\n Bus Address Latch Enable. The address bus is latched on the BCLK<\/strong><\/p>\n Bus Clock, 33% Duty Cycle. Frequency Varies. 4.77 to 8 MHz DACKx<\/strong><\/p>\n DMA Acknowledge. The active-low DMA Acknowledge 0 to 3 and 5 DRQx<\/strong><\/p>\n DMA Request. These signals are asynchronous channel requests IOCS16<\/strong><\/p>\n I\/O size 16. Generated by a 16 bit slave when addressed by a I\/O CH CK<\/strong><\/p>\n Channel Check. A low signal generates an NMI. The NMI signal I\/O CH RDY<\/strong><\/p>\n Channel Ready. Setting this low prevents the default ready IOR<\/strong><\/p>\n The I\/O Read is an active-low signal which instructs the I\/O IOW<\/strong><\/p>\n The I\/O Write is an active-low signal which instructs the I\/O IRQx<\/strong><\/p>\n Interrupt Request. IRQ2 has the highest priority. IRQ 10-15 LAxx<\/strong><\/p>\n Latchable Address lines. Combine with the lower address lines MASTER<\/strong><\/p>\n 16 bit bus master. Generated by the ISA bus master when MEMCS16<\/strong><\/p>\n The active-low Memory Chip Select 16 indicates that the MEMR<\/strong><\/p>\n The Memory Read is an active-low signal which instructs memory MEMW<\/strong><\/p>\n The Memory Write is an active-low signal which instructs NOWS<\/strong><\/p>\n No Wait State. Used to shorten the number of wait states OSC<\/strong><\/p>\n Oscillator, 14.31818 MHz, 50% Duty Cycle. Frequency varies. REFRESH<\/strong><\/p>\n Refresh. Generated when the refresh logic is bus master. This RESET<\/strong><\/p>\n This signal goes low when the machine is powered up. Driving SA0-SA19<\/strong><\/p>\n System Address Lines, tri-state. The System Address lines run SBHE<\/strong><\/p>\n System Bus High Enable, tri-state. Indicates a 16 bit data SD0-SD16<\/strong><\/p>\n System Data lines, or Standard Data Lines. They are SMEMR<\/strong><\/p>\n System Memory Read Command line. Indicates a memory read in SMEMW<\/strong><\/p>\n System Memory Write Commmand line. Indicates a memory write in T\/C<\/strong><\/p>\n Terminal Count. Notifies the cpu that that the last DMA data 8 Bit Memory or I\/O Transfer Timing Diagram (4 wait states __ __ __ __ __ __ __ AEN __________________________________________________<\/p>\n ______________________________________ ___________________________________ Note: W1 through W4 indicate wait cycles.<\/p>\n BALE is placed high, and the address is latched on the SA bus. The command line is then pulled low (IORC or IOWC for I\/O NOWS is sampled at the midpoint of each wait cycle. If it is The default for 8 bit transfers is 4 wait states. Some 16 Bit Memory or I\/O Transfer Timing Diagram (1 wait state __ __ __ __ __ __ _____________ __ ________________ _______ __________________ _________________ ____________________ _________________ ___________ _________________ ___________ ______________ An asterisk (*) denotes the point where the signal is sampled.<\/p>\n [1] The portion of the address on the LA bus for the NEXT [2] AEN remains low throughout the entire transfer cycle, [3] Some bus controllers sample this signal during the same [4] M16 is sampled a second time, in case the adapter card did 16 bit transfers follow the same basic timing as 8 bit I\/O adapter cards do not need to monitor the LA bus or BALE, SBHE will be pulled low by the system board, and the adapter For read operations, the data is sampled on the rising edge of The default for 16 bit transfers is 1 wait state. This may be SMRDC\/SMWTC follow the same timing as MRDC\/MWTC respectively It is also possible for an 8 bit bus cycle to use the upper Shortening or Lengthening the bus cycle:<\/strong><\/p>\n BCLK W W W W |—Transfer 1——|—-Transfer 2———|—-Transfer 3—|<\/p>\n BALE CHRDY NOWS An asterisk (*) denotes the point where the signal is sampled. This timing diagram shows three different transfer cycles. The I\/O Port Addresses<\/strong><\/p>\n Note: Only the first 10 address lines are decoded for I\/O Port (hex) 000-00F 010-01F 020-02F 030-03F 040-05F 060-06F 070-071 080-083 090-097 0A0-0AF 0C0-0CF 0E0-0EF 0F0-0FF 100-10F 110-16F 170-17F 180-1EF 1F0-1FF 200-20F 210-217 220-26F 278-27F 280-2A1 2A2-2A3 2B0-2DF 2E2-2E3 2E8-2EF 2F0-2F7 2F8-2FF 300-31F 320-32F 330-33F 340-35F 360-36F 370-377 378-37F 380-38F 390-39F 3A0-3AF 3B0-3BF 3BC-3BF 3C0-3CF 3D0-3DF 3E0-3EF 3F0-3F7 3F8-3FF Soundblaster cards usually use I\/O ports 220-22F. DMA Read and Write<\/strong><\/p>\n The ISA bus uses two DMA controllers (DMAC) cascaded together. The DMAC can be programmed for read transfers (data is read Before a DMA transfer can take place, the DMA Controller Slave DMA Controller<\/strong><\/p>\n I\/O 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0081 0082 0083 0087 0089 008A 008B Master DMA Controller<\/strong><\/p>\n I\/O 00C0 00C2 00C4 00C6 00C8 00CA 00CC 00CE 00D0 00D2 00D4 00D6 00D8 00DA 00DC 00DE Single Transfer Mode<\/strong><\/p>\n The DMAC is programmed for transfer. The DMA device requests a The DMAC places the memory address on the SA bus (at the same __ __ __ __ __ __ _______ ______________________________ _______ ________ ____________________________ ____________________________ Block Transfer Mode<\/strong><\/p>\n The DMAC is programmed for transfer. The device attempting DMA Note: Block transfer must be used carefully. The bus cannot be Demand Transfer Mode<\/strong><\/p>\n The DMAC is programmed for transfer. The device attempting DMA Interrupts on the ISA bus<\/strong><\/p>\n Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ0,1,2,8, and 13 are not available on the ISA bus.<\/p>\n The IBM PC and XT had only a single 8259 interrupt controller. The software aspects of interrupts and interrupt handlers is Bus Mastering:<\/strong><\/p>\n An ISA device may take control of the bus, but this must be To take control of the bus, the device first asserts its DRQ Contributor:<\/i>
\nthe first 62 pins and 16-bit cards uses all 98 pins. Some 8-bit
\ncards uses some of the 16-bit extension pins to get more
\ninterrupts.<\/p>\n![](\"https:\/\/skilx.cc\/radio\/wp-content\/uploads\/57506760df7031c9d8e3b853e093bcdd.gif\")
(at
\nthe card)
\n![](\"https:\/\/skilx.cc\/radio\/wp-content\/uploads\/487df16efec75117ca264596c151559e.gif\")
(at
\nthe computer)<\/p>\n![](\"https:\/\/skilx.cc\/radio\/wp-content\/uploads\/48f2a6df6e65246fb74ae8c79c38283d.gif\")
(at
\nthe card)
\n![](\"https:\/\/skilx.cc\/radio\/wp-content\/uploads\/77a98287d496030a8cad9de63a6a009b.gif\")
(at the computer)<\/p>\n
\nthe bus. This prevents an I\/O device from responding to the I\/O
\ncommand lines during a DMA transfer. When AEN is active, the DMA
\nController has control of the address bus as the memory and I\/O
\nread\/write command lines.<\/p>\n
\nrising edge of this signal. The address on the SA bus is valid
\nfrom the falling edge of BALE to the end of the bus cycle. Memory
\ndevices should latch the LA bus on the falling edge of BALE. Some
\nreferences refer to this signal as Buffered Address Latch Enable,
\nor just Address Latch Enable (ALE). The Buffered-Address Latch
\nEnable is used to latch SA0-19 on the falling edge. This signal
\nis forced high during DMA cycles.<\/p>\n
\ntypical. 8.3 MHz is specified as the maximum, but many systems
\nallow this clock to be set to 12 MHz and higher.<\/p>\n
\nto 7 are the corresponding acknowledge signals for DRQ 0-3, 5-7.<\/p>\n
\nused by I\/O channel devices to gain DMA service. DMA request
\nchannels 0-3 are for 8-bit data transfer. DAM request channels
\n5-7 are for 16-bit data transfer. DMA request channel 4 is used
\ninternally on the system board. DMA requests should be held high
\nuntil the corresponding DACK line goes active. DMA requests are
\nserviced in the following priority sequence:
\nHigh: DRQ 0, 1, 2, 3, 5, 6, 7 Lowest<\/p>\n
\nbus master. The active-low I\/O Chip Select 16 indicates that the
\ncurrent transfer is a 1 wait state, 16 bit I\/O cycle. Open
\nCollector.<\/p>\n
\ncan be masked on a PC, externally to the processor (of course).
\nBit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port
\n61 (hex) (recognition of channel check) must both be set to zero
\nfor an NMI to reach the cpu. The I\/O Channel Check is an
\nactive-low signal which indicates that a parity error exists in a
\ndevice on the I\/O channel.<\/p>\n
\ntimer from timing out. The slave device may then set it high
\nagain when it is ready to end the bus cycle. Holding this line
\nlow for too long (15 microseconds, typical) can prevent RAM
\nrefresh cycles on some systems. This signal is called IOCHRDY
\n(I\/O Channel Ready) by some references. CHRDY and NOWS should not
\nbe used simultaneously. This may cause problems with some bus
\ncontrollers. This signal is pulled low by a memory or I\/O device
\nto lengthen memory or I\/O read\/write cycles. It should only be
\nheld low for a minimum of 2.5 microseconds.<\/p>\n
\ndevice to drive its data onto the data bus, SD0-SD15.<\/p>\n
\ndevice to read data from the data bus, SD0-SD15.<\/p>\n
\nare only available on AT machines, and are higher priority than
\nIRQ 3-7. The Interrupt Request signals which indicate I\/O service
\nattention. They are prioritized in the following sequence:
\nHighest IRQ 9(2),10,11,12,14,3,4,5,6,7<\/p>\n
\nto form a 24 bit address space (16 MB) These unlatched address
\nsignals give the system up to 16 MB of address ability. The are
\nvalid when "BALE" is high.<\/p>\n
\ninitiating a bus cycle. This active-low signal is used in
\nconjunction with a DRQ line by a processor on the I\/O channel to
\ngain control of the system. The I\/O processor first issues a DRQ,
\nand upon receiving the corresponding DACK, the I\/O processor may
\nassert MASTER, which will allow it to control the system address,
\ndata and control lines. This signal should not be asserted for
\nmore than 15 microseconds, or system memory may be corrupted du
\nto the lack of memory refresh activity.<\/p>\n
\ncurrent data transfer is a 1 wait state, 16 bit data memory
\ncycle.<\/p>\n
\ndevices to drive data onto the data bus SD0-SD15. This signal is
\nactive on all memory read cycles.<\/p>\n
\nmemory devices to store data present on the data bus SD0-SD15.
\nThis signal is active on all memory write cycles.<\/p>\n
\ngenerated by the default ready timer. This causes the bus cycle
\nto end more quickly, since wait states will not be inserted. Most
\nsystems will ignore NOWS if CHRDY is active (low). However, this
\nmay cause problems with some bus controllers, and both signals
\nshould not be active simultaneously.<\/p>\n
\nThis was originally divided by 3 to provide the 4.77 MHz cpu
\nclock of early PCs, and divided by 12 to produce the 1.19 MHz
\nsystem clock. Some references have placed this signal as low as 1
\nMHz (possibly referencing the system clock), but most modern
\nsystems use 14.318 MHz.
\nThis frequency (14.318 MHz) is four times the television
\ncolorburst frequency. Refresh timing on many PC’s is based on
\nOSC\/18, or approximately one refresh cycle every 15 microseconds.
\nMany modern motherboards allow this rate to be changed, which
\nfrees up some bus cycles for use by software, but also can cause
\nmemory errors if the system RAM cannot handle the slower refresh
\nrates.<\/p>\n
\nactive-low signal is used to indicate a memory refresh cycle is
\nin progress. An ISA device acting as bus master may also use this
\nsignal to initiate a refresh cycle.<\/p>\n
\nit low will force a system reset. This signal goes high to reset
\nthe system during powerup, low line-voltage or hardware reset.
\n??????????????<\/p>\n
\nfrom bit 0 to bit 19. They are latched on to the falling edge of
\n"BALE".<\/p>\n
\ntransfer. The System Bus High Enable indicates high byte transfer
\nis occurring on the data bus SD8-SD15. This may also indicate an
\n8 bit transfer using the upper half of the bus data (if an odd
\naddress is present).<\/p>\n
\nbidrectional and tri-state. On most systems, the data lines float
\nhigh when not driven. These 16 lines provide for data transfer
\nbetween the processor, memory and I\/O devices.<\/p>\n
\nthe lower 1 MB area. This System Memory Read is an active-low
\nsignal which instructs memory devices to drive data onto the data
\nbus SD0-SD15. This signal is active only when the memory address
\nis within the lowest 1MB of memory address space.<\/p>\n
\nthe lower 1 MB area. The System Memory Write is an active-low
\nsignal which instructs memory devices to store data preset on the
\ndata bus SD0-SD15. This signal is active only when the memory
\naddress is within the lowest 1MB of memory address space.<\/p>\n
\ntransfer operation is complete. Terminal Count provides a pulse
\nwhen the terminal count for any DMA channel is reached.<\/p>\n
\nshown)<\/strong><\/p>\n
\nBCLK ___| |___| |___| |__| |___| |___| |___| |__
\n W1 W2 W3 W4
\n __
\nBALE _______| |_______________________________________<\/p>\n
\nSA0-SA19 ———<______________________________________>-
\n _____________ _____
\nCommand Line |______________________________|
\n(IORC,IOWC,
\nSMRDC, or SMWTC)
\n _____
\nSD0-SD7 —————————————<_____>—-
\n(READ)<\/p>\n
\nSD0-SD7 ———<___________________________________>—-
\n(WRITE)<\/p>\n
\nThe slave device may safely sample the address during the falling
\nedge of BALE, and the address on the SA bus remains valid until
\nthe end of the transfer cycle. Note that AEN remains low
\nthroughout the entire transfer cycle.<\/p>\n
\ncommands, SMRDSC or SMWTC for memory commands, read and write
\nrespectively). For write operations, the data remains on the SD
\nbus for the remainder of the transfer cycle. For read operations,
\nthe data must be valid on the falling edge of the last cycle.<\/p>\n
\nlow, the transfer cycle terminates without further wait states.
\nCHRDY is sampled during the first half of the clock cycle. If it
\nis low, further wait cycles will be inserted.<\/p>\n
\ncomputers allow the number of default wait states to be changed.<\/p>\n
\nshown)<\/strong><\/p>\n
\nBCLK ___| |___| |___| |__| |___| |___| |_
\nAEN [2] __________________________________________<\/p>\n
\nLA17-LA23 ——-<_____________>-[1]——————<\/p>\n
\nBALE ______________| |________________________<\/p>\n
\nSBHE |__________________|<\/p>\n
\nSA0-SA19 —————<__________________>——-<\/p>\n
\nM16 |____|
\n * * [4]<\/p>\n
\nIO16 [3] |_____________|
\n *<\/p>\n
\nCommand Line |____________|
\n(IORC,IOWC,
\nMRDC, or MWTC)
\n ____
\nSD0-SD7 —————————<____>———
\n(READ)<\/p>\n
\nSD0-SD7 ——————<______________>———
\n(WRITE)<\/p>\n
\ncycle may now be placed on the bus. This is used so that cards
\nmay begin decoding the address early. Address pipelining must be
\nactive.<\/p>\n
\nindicating that a normal (non-DMA) transfer is occurring.<\/p>\n
\nclock cycle as M16, instead of during the first wait state, as
\nshown above. In this case, IO16 needs to be pulled low as soon as
\nthe address is decoded, which is before the I\/O command lines are
\nactive.<\/p>\n
\nnot active the signal in time for the first sample (usually
\nbecause the memory device is not monitoring the LA bus for early
\naddress information, or is waiting for the falling edge of BALE).<\/p>\n
\ntransfers. A valid address may appear on the LA bus prior to the
\nbeginning of the transfer cycle. Unlike the SA bus, the LA bus is
\nnot latched, and is not valid for the entire transfer cycle (on
\nmost computers). The LA bus should be latched on the falling edge
\nof BALE. Note that on some systems, the LA bus signals will
\nfollow the same timing as the SA bus. On either type of system, a
\nvalid address is present on the falling edge of BALE.<\/p>\n
\nsince I\/O addresses are always within the address space of the SA
\nbus.<\/p>\n
\ncard must respond with IO16 or M16 at the appropriate time, or
\nelse the transfer will be split into two separate 8 bit
\ntransfers. Many systems expect IO16 or M16 before the command
\nlines are valid. This requires that IO16 or M16 be pulled low as
\nsoon as the address is decoded (before it is known whether the
\ncycle is I\/O or Memory). If the system is starting a memory
\ncycle, it will ignore IO16 (and vice-versa for I\/O cycles and
\nM16).<\/p>\n
\nthe last clock cycle. For write operations, valid data appears on
\nthe bus before the end of the cycle, as shown in the timing
\ndiagram. While the timing diagram indicates that the data needs
\nto be sampled on the rising clock, on most systems it remains
\nvalid for the entire clock cycle.<\/p>\n
\nshortened or lengthened in the same manner as 8 bit transfers,
\nvia NOWS and CHRDY. Many systems only allow 16 bit memory devices
\n(and not I\/O devices) to transfer using 0 wait states (NOWS has
\nno effect on 16 bit I\/O cycles).<\/p>\n
\nwhen the address is within the lower 1 MB. If the address is not
\nwithin the lower 1 MB boundary, SMRDC\/SMWTC will remain high
\nduring the entire cycle.<\/p>\n
\nportion of the bus. In this case, the timing will be similar to a
\n16 bit cycle, but an odd address will be present on the bus. This
\nmeans that the bus is transferring 8 bits using the upper data
\nbits (SD8-SD15).<\/p>\n
\n _ __ __ __ __ __ __ __ __ __ __ __
\n |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__<\/p>\n
\n __ __ __ __
\n________| |______________| |____________________| |______________|
\nSBHE
\n_________ _______________________
\n |__________________|__________________|
\nSA0-SA19
\n _________________ _____________________ _________________
\n———-<_________________><_____________________><_________________>
\nIO16
\n___________ ___ ___________________________
\n |_____________| |_____________|
\n * *<\/p>\n
\n________________________________ _______________________________
\n |______|
\n * * * [1]<\/p>\n
\n______________________________________________________ _____
\n |__________|
\n * [2]
\nIORC
\n______________ _______ _______ ____
\n |_________| |_______________| |_________|
\nSD0-SD15
\n ____ ____ ____
\n———————<____>——————<____>————<____>—
\n * * *<\/p>\n
\nW=Wait Cycle<\/p>\n
\nfirst is a 16 bit standard I\/O read. This is followed by an
\nalmost identical 16 bit I\/O read, with one wait state inserted.
\nThe I\/O device pulls CHRDY low to indicate that it is not ready
\nto complete the transfer (see [1]). This inserts a wait cycle,
\nand CHRDY is again sampled. At this second sample, the I\/O device
\nhas completed its operation and released CHRDY, and the bus cycle
\nnow terminates. The third cycle is an 8 bit transfer, which is
\nshortened to 1 wait state (the default is 4) by the use of NOWS.<\/p>\n
\noperations. This limits the I\/O address space to address 3FF
\n(hex) and lower. Some systems allow for 16 bit I\/O address space,
\nbut may be limited due to some I\/O cards only decoding 10 of
\nthese 16 bits.<\/p>\n
\n Port Assignments<\/p>\n
\n DMA Controller<\/p>\n
\n DMA Controller (PS\/2)<\/p>\n
\n Master Programmable Interrupt Controller (PIC)<\/p>\n
\n Slave PIC<\/p>\n
\n Programmable Interval Timer (PIT)<\/p>\n
\n Keyboard Controller<\/p>\n
\n Real Time Clock<\/p>\n
\n DMA Page Register<\/p>\n
\n Programmable Option Select (PS\/2)<\/p>\n
\n PIC #2<\/p>\n
\n DMAC #2<\/p>\n
\n reserved<\/p>\n
\n Math coprocessor, PCJr Disk Controller<\/p>\n
\n Programmable Option Select (PS\/2)<\/p>\n
\n AVAILABLE<\/p>\n
\n Hard Drive 1 (AT)<\/p>\n
\n AVAILABLE<\/p>\n
\n Hard Drive 0 (AT)<\/p>\n
\n Game Adapter<\/p>\n
\n Expansion Card Ports<\/p>\n
\n AVAILABLE<\/p>\n
\n Parallel Port 3<\/p>\n
\n AVAILABLE<\/p>\n
\n clock<\/p>\n
\n EGA\/Video<\/p>\n
\n Data Acquisition Adapter (AT)<\/p>\n
\n Serial Port COM4<\/p>\n
\n Reserved<\/p>\n
\n Serial Port COM2<\/p>\n
\n Prototype Adapter, Periscope Hardware Debugger<\/p>\n
\n AVAILABLE<\/p>\n
\n Reserved for XT\/370<\/p>\n
\n AVAILABLE<\/p>\n
\n Network<\/p>\n
\n Floppy Disk Controller<\/p>\n
\n Parallel Port 2<\/p>\n
\n SDLC Adapter<\/p>\n
\n Cluster Adapter<\/p>\n
\n reserved<\/p>\n
\n Monochrome Adapter<\/p>\n
\n Parallel Port 1<\/p>\n
\n EGA\/VGA<\/p>\n
\n Color Graphics Adapter<\/p>\n
\n Serial Port COM3<\/p>\n
\n Floppy Disk Controller<\/p>\n
\n Serial Port COM1<\/p>\n
\nData acquisition cards frequently use 300-31F.<\/p>\n
\nThe slave DMAC connects to the master DMAC via DMA channel 4
\n(channel 0 on the master DMAC). The slave therefore gains control
\nof the bus through the master DMAC. On the ISA bus, the DMAC is
\nprogrammed to use fixed priority (channel 0 always has the
\nhighest priority), which means that channel 0-4 from the slave
\nhave the highest priority (since they connect to the master
\nchannel 0), followed by channels 5-7 (which are channel 1-3 on
\nthe master).<\/p>\n
\nfrom memory and written to the I\/O device), write transfers (data
\nis read from the I\/O device and written to memory), or verify
\ntransfers (neither a read or a write — this was used by DMA CH0
\nfor DRAM refresh on early PCs).<\/p>\n
\n(DMAC) must be programmed. This is done by writing the start
\naddress and the number of bytes to transfer (called the transfer
\ncount) and the direction of the transfer to the DMAC. After the
\nDMAC has been programmed, the device may activate the appropriate
\nDMA request (DRQx) line.<\/p>\n
\n Port<\/p>\n
\n DMA CH0 Memory Address Register
\n Contains the lower 16 bits of the memory address, written
\n as two consecutive bytes.<\/p>\n
\n DMA CH0 Transfer Count
\n Contains the lower 16 bits of the transfer count, written
\n as two consecutive bytes.<\/p>\n
\n DMA CH1 Memory Address Register<\/p>\n
\n DMA CH1 Transfer Count<\/p>\n
\n DMA CH2 Memory Address Register<\/p>\n
\n DMA CH2 Transfer Count<\/p>\n
\n DMA CH3 Memory Address Register<\/p>\n
\n DMA CH3 Transfer Count<\/p>\n
\n DMAC Status\/Control Register
\n Status (I\/O read) bits 0-3: Terminal Count, CH 0-3
\n — bits 4-7: Request CH0-3
\n Control (write)
\n — bit 0: Mem to mem enable (1 = enabled)
\n — bit 1: ch0 address hold enable (1 = enabled)
\n — bit 2: controller disable (1 = disabled)
\n — bit 3: timing (0 = normal, 1 = compressed)
\n — bit 4: priority (0 = fixed, 1 = rotating)
\n — bit 5: write selection (0 = late, 1 = extended)
\n — bit 6: DRQx sense asserted (0 = high, 1 = low)
\n — bit 7: DAKn sense asserted (0 = low, 1 = high)<\/p>\n
\n Software DRQn Request
\n — bits 0-1: channel select (CH0-3)
\n — bit 2: request bit (0 = reset, 1 = set)<\/p>\n
\n DMA mask register
\n — bits 0-1: channel select (CH0-3)
\n — bit 2: mask bit (0 = reset, 1 = set)<\/p>\n
\n DMA Mode Register
\n — bits 0-1: channel select (CH0-3)
\n — bits 2-3: 00 = verify transfer, 01 = write transfer, 10
\n = read transfer, 11 = reserved
\n — bit 4: Auto init (0 = disabled, 1 = enabled)
\n — bit 5: Address (0 = increment, 1 = decrement)
\n — bits 6-7: 00 = demand transfer mode, 01 = single
\n transfer mode, 10 = block transfer mode, 11 = cascade
\n mode<\/p>\n
\n DMA Clear Byte Pointer
\n Writing to this causes the DMAC to clear the pointer used
\n to keep track of 16 bit data transfers into and out of
\n the DMAC for hi\/low byte sequencing.<\/p>\n
\n DMA Master Clear (Hardware Reset)<\/p>\n
\n DMA Reset Mask Register — clears the mask register<\/p>\n
\n DMA Mask Register
\n — bits 0-3: mask bits for CH0-3 (0 = not masked, 1 =
\n masked)<\/p>\n
\n DMA CH2 Page Register (address bits A16-A23)<\/p>\n
\n DMA CH3 Page Register<\/p>\n
\n DMA CH1 Page Register<\/p>\n
\n DMA CH0 Page Register<\/p>\n
\n DMA CH6 Page Register<\/p>\n
\n DMA CH7 Page Register<\/p>\n
\n DMA CH5 Page Register<\/p>\n
\n Port<\/p>\n
\n DMA CH4 Memory Address Register
\n Contains the lower 16 bits of the memory address, written
\n as two consecutive bytes.<\/p>\n
\n DMA CH4 Transfer Count
\n Contains the lower 16 bits of the transfer count, written
\n as two consecutive bytes.<\/p>\n
\n DMA CH5 Memory Address Register<\/p>\n
\n DMA CH5 Transfer Count<\/p>\n
\n DMA CH6 Memory Address Register<\/p>\n
\n DMA CH6 Transfer Count<\/p>\n
\n DMA CH7 Memory Address Register<\/p>\n
\n DMA CH7 Transfer Count<\/p>\n
\n DMAC Status\/Control Register
\n Status (I\/O read) bits 0-3: Terminal Count, CH 4-7
\n — bits 4-7: Request CH4-7
\n Control (write)- bit 0: Mem to mem enable (1 = enabled)
\n — bit 1: ch0 address hold enable (1 = enabled)
\n — bit 2: controller disable (1 = disabled)
\n — bit 3: timing (0 = normal, 1 = compressed)
\n — bit 4: priority (0 = fixed, 1 = rotating)
\n — bit 5: write selection (0 = late, 1 = extended)
\n — bit 6: DRQx sense asserted (0 = high, 1 = low)
\n — bit 7: DAKn sense asserted (0 = low, 1 = high)<\/p>\n
\n Software DRQn Request
\n — bits 0-1: channel select (CH4-7)
\n — bit 2: request bit (0 = reset, 1 = set)<\/p>\n
\n DMA mask register
\n — bits 0-1: channel select (CH4-7)
\n — bit 2: mask bit (0 = reset, 1 = set)<\/p>\n
\n DMA Mode Register
\n — bits 0-1: channel select (CH4-7)
\n — bits 2-3: 00 = verify transfer, 01 = write transfer, 10
\n = read transfer, 11 = reserved
\n — bit 4: Auto init (0 = disabled, 1 = enabled)
\n — bit 5: Address (0 = increment, 1 = decrement)
\n — bits 6-7: 00 = demand transfer mode, 01 = single
\n transfer mode, 10 = block transfer mode, 11 = cascade
\n mode<\/p>\n
\n DMA Clear Byte Pointer
\n Writing to this causes the DMAC to clear the pointer used
\n to keep track of 16 bit data transfers into and out of
\n the DMAC for hi\/low byte sequencing.<\/p>\n
\n DMA Master Clear (Hardware Reset)<\/p>\n
\n DMA Reset Mask Register — clears the mask register<\/p>\n
\n DMA Mask Register
\n — bits 0-3: mask bits for CH4-7 (0 = not masked, 1 =
\n masked)<\/p>\n
\ntransfer by driving the appropriate DRQ line high. The DMAC
\nresponds by asserting AEN and acknowledges the DMA request
\nthrough the appropriate DAK line. The I\/O and memory command
\nlines are also asserted. When the DMA device sees the DAK signal,
\nit drops the DRQ line.<\/p>\n
\ntime as the command lines are asserted), and the device either
\nreads from or writes to memory, depending on the type of
\ntransfer. The transfer count is incremented, and the address
\nincremented\/decremented. DAK is de-asserted. The cpu now once
\nagain has control of the bus, and continues execution until the
\nI\/O device is once again ready for transfer. The DMA device
\nrepeats the procedure, driving DRQ high and waiting for DAK, then
\ntransferring data. This continues for a number of cycles equal to
\nthe transfer count. When this has been completed, the DMAC
\nsignals the cpu that the DMA transfer is complete via the TC
\n(terminal count) signal.<\/p>\n
\nBCLK ___| |___| |___| |__| |___| |___| |___<\/p>\n
\nDRQx _| |___________________________________<\/p>\n
\nAEN ____| |________<\/p>\n
\nDAKx |___________________________|<\/p>\n
\nSA0-SA15 ——-<____________________________>——-
\n ___________ ____________
\nCommand Line |___________________|
\n(IORC, MRDC)
\n _____________
\nSD0-SD7 ———————-<_____________>——-
\n(READ)<\/p>\n
\nSD0-SD7 ——-<____________________________>——-
\n(WRITE)<\/p>\n
\ntransfer drives the appropriate DRQ line high. The motherboard
\nresponds by driving AEN high and DAK low. This indicates that the
\nDMA device is now the bus master. In response to the DAK signal,
\nthe DMA device drops DRQ. The DMAC places the address for DMA
\ntransfer on the address bus. Both the memory and I\/O command
\nlines are asserted (since DMA involves both an I\/O and a memory
\ndevice). AEN prevents I\/O devices from responding to the I\/O
\ncommand lines, which would not result in proper operation since
\nthe I\/O lines are active, but a memory address is on the address
\nbus. The data transfer is now done (memory read or write), and
\nthe DMAC increments\/decrements the address and begins another
\ncycle. This continues for a number of cycles equal to the DMAC
\ntransfer count. When this has been completed, the terminal count
\nsignal (TC) is generated by the DMAC to inform the cpu that the
\nDMA transfer has been completed.<\/p>\n
\nused for other things (like RAM refresh) while block mode
\ntransfers are being done.<\/p>\n
\ntransfer drives the appropriate DRQ line high. The motherboard
\nresponds by driving AEN high and DAK low. This indicates that the
\nDMA device is now the bus master. Unlike single transfer and
\nblock transfer, the DMA device does not drop DRQ in response to
\nDAK. The DMA device transfers data in the same manner as for
\nblock transfers. The DMAC will continue to generate DMA cycles as
\nlong as the I\/O device asserts DRQ. When the I\/O device is unable
\nto continue the transfer (if it no longer had data ready to
\ntransfer, for example), it drops DRQ and the cpu once again has
\ncontrol of the bus. Control is returned to the DMAC by once again
\nasserting DRQ. This continues until the terminal count has been
\nreached, and the TC signal informs the cpu that the transfer has
\nbeen completed.<\/p>\n
\n Interrupt
\n Description<\/p>\n
\n 2
\n Parity Error, Mem Refresh<\/p>\n
\n 8
\n 8253 Channel 0 (System Timer)<\/p>\n
\n 9
\n Keyboard<\/p>\n
\n A
\n Cascade from slave PIC<\/p>\n
\n B
\n COM2<\/p>\n
\n C
\n COM1<\/p>\n
\n D
\n LPT2<\/p>\n
\n E
\n Floppy Drive Controller<\/p>\n
\n F
\n LPT1<\/p>\n
\n F
\n Real Time Clock<\/p>\n
\n F
\n Redirection to IRQ2<\/p>\n
\n F
\n Reserved<\/p>\n
\n F
\n Reserved<\/p>\n
\n F
\n Mouse Interface<\/p>\n
\n F
\n Coprocessor<\/p>\n
\n F
\n Hard Drive Controller<\/p>\n
\n F
\n Reserved<\/p>\n
\nThe AT and later machines have a second interrupt controller, and
\nthe two are used in a master\/slave combination. IRQ2 and IRQ9 are
\nthe same pin on most ISA systems. Interrupts on most systems may
\nbe either edge triggered or level triggered. The default is
\nusually edge triggered, and active high (low to high transition).
\nThe interrupt level must be held high until the first interrupt
\nacknowledge cycle (two interrupt acknowledge bus cycles are
\ngenerated in response to an interrupt request).<\/p>\n
\nintentionally omitted from this document, due to the numerous
\nsyntactical differences in software tools and the fact that
\nadequate documentation of this topic is usually provided with
\ndevelopement software.<\/p>\n
\ndone with caution. There are no safety mechanisms involved, and
\nso it is easily possible to crash the entire system by
\nincorrectly taking control of the bus. For example, most systems
\nrequire bus cycles for DRAM refresh. If the ISA bus master does
\nnot relinquish control of the bus or generate its own DRAM
\nrefresh cycles every 15 microseconds, the system RAM can become
\ncorrupted. The ISA adapter card can generate refresh cycles
\nwithout relinquishing control of the bus by asserting REFRESH.
\nMRDC can be then monitored to determine when the refresh cycle
\nends.<\/p>\n
\nline. The DMAC sends a hold request to the cpu, and when the DMAC
\nreceives a hold acknowledge, it asserts the appropriate DAK line
\ncorresponding to the DRQ line asserted. The device is now the bus
\nmaster. AEN is asserted, so if the device wishes to access I\/O
\ndevices, it must assert MASTER16 to release AEN. Control of the
\nbus is returned to the system board by releasing DRQ.<\/p>\n
\n
\n Joakim \u0426gren,
\n Niklas Edmundsson<\/a>,
\n Mark Sokos<\/a>,
\n Pieter Hollants<\/a>
\n<\/i><\/p>\n